Keyphrases
Test Case Generation
80%
N-detect
52%
Zero-suppressed Binary Decision Diagram
42%
Fault Model
35%
Test Set Embedding
32%
Propagation Path
30%
Path Segment
28%
Transition Faults
26%
Fault Test
25%
Low Power Test
23%
Digital Circuits
23%
Multicore Systems
22%
Fault Coverage
22%
Parallelization
21%
Test Set Size
21%
Path Delay Faults
20%
Embedding Scheme
19%
Optimal Variables
19%
Path Representation
19%
Variable Ordering
19%
Popular
19%
Shared Memory
19%
Path Correlation
19%
Circuit Size
19%
Multiple Fault Detection
17%
Path Enumeration
17%
Deterministic Test
16%
Parallel Implementation
16%
Compact Test
15%
Test Functions
15%
Stuck-at
15%
Directed Acyclic Graph
14%
Fault Simulation
14%
Design Automation
14%
Proposed Methodology
14%
Reduction Rate
13%
Bit Reduction
13%
Dynamic Method
13%
Dynamic Compaction
13%
Detection Test
13%
Processing Speed
13%
Multiplex Detection
13%
Communication Rate
13%
Primitive Path
13%
Measurement Path
13%
Execution Time
13%
Sensor Networks
13%
Compaction
13%
Rate Requirement
13%
Ocean Sound
13%
Computer Science
Experimental Result
100%
Test Generation
72%
binary decision diagram
54%
Propagation Path
52%
Fault Coverage
37%
Digital Circuit
32%
Multicore System
28%
Systematic Methodology
26%
Relaxation Method
19%
Test Compression
19%
Speed-up
19%
Path Representation
19%
linear-feedback shift register
19%
Fault detection
19%
Internet-Of-Things
19%
Fault Simulation
16%
Multicore
16%
Parallel Implementation
16%
Computer Hardware
16%
Shared Memory (Multicore)
15%
Storage Requirement
15%
Directed Acyclic Graph
14%
Related Application
13%
Benchmark Circuit
13%
Fixed Delay Model
13%
Execution Time
13%
Criticality
13%
Exact Algorithm
13%
Input/Output
13%
Sensor Networks
13%
Design Automation
11%
Parallelization
11%
information acquisition
9%
Parallelism
9%
Processing Power
8%
Timing Analysis
7%
Custom Hardware
6%
Memory Requirement
6%
Memory Resource
6%
Multiprocessor System
6%
Shared Memory Multiprocessor
6%
Processing Core
6%
Parallel Fault Simulation
6%
Parallel Solution
6%
Testing Process
6%
Estimation Performance
6%
Test Automation
6%
Partitioning Technique
6%
Serial Algorithm
6%
Integrated Circuit
6%
Engineering
Experimental Result
65%
Propagation Path
52%
Fault Model
41%
Digital Circuits
32%
Systematic Methodology
26%
Applicability
22%
Built-in Self Test
19%
Internet-Of-Things
19%
Storage Requirement
15%
Nodes
14%
Initial Test
13%
Related Application
13%
Subcircuit
13%
Dependability
13%
Sensor Network
13%
Digital Electronics
13%
Test Analysis
6%
Design Process
6%
Path Error
6%
Operating Characteristic
6%
Product Design
6%
Nanoscale
6%
Output Circuit
6%
VLSI Circuits
6%
Electronic Design Automation
6%
Efficient Representation
6%
Design Verification
6%
Linear Size
6%
Pathlength
6%
Critical Path
6%
