TY - JOUR
T1 - A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems
AU - Savva, Andreas G.
AU - Theocharides, Theocharis
AU - Nicopoulos, Chrysostomos
N1 - Publisher Copyright:
© 2017 Andreas G. Savva et al.
PY - 2017
Y1 - 2017
N2 - This work presents a design exploration framework for developing a high level Artificial Neural Network (ANN) for fault detection in hardware systems. ANNs can be used for fault detection purposes since they have excellent characteristics such as generalization capability, robustness, and fault tolerance. Designing an ANN in order to be used for fault detection purposes includes different parameters. Through this work, those parameters are presented and analyzed based on simulations. Moreover, after the development of the ANN, in order to evaluate it, a case study scenario based on Networks on Chip is used for detection of interrouter link faults. Simulation results with various synthetic traffic models show that the proposed work can detect up to 96-99% of interrouter link faults with a delay less than 60 cycles. Added to this, the size of the ANN is kept relatively small and they can be implemented in hardware easily. Synthesis results indicate an estimated amount of 0.0523 mW power consumption per neuron for the implemented ANN when computing a complete cycle.
AB - This work presents a design exploration framework for developing a high level Artificial Neural Network (ANN) for fault detection in hardware systems. ANNs can be used for fault detection purposes since they have excellent characteristics such as generalization capability, robustness, and fault tolerance. Designing an ANN in order to be used for fault detection purposes includes different parameters. Through this work, those parameters are presented and analyzed based on simulations. Moreover, after the development of the ANN, in order to evaluate it, a case study scenario based on Networks on Chip is used for detection of interrouter link faults. Simulation results with various synthetic traffic models show that the proposed work can detect up to 96-99% of interrouter link faults with a delay less than 60 cycles. Added to this, the size of the ANN is kept relatively small and they can be implemented in hardware easily. Synthesis results indicate an estimated amount of 0.0523 mW power consumption per neuron for the implemented ANN when computing a complete cycle.
UR - http://www.scopus.com/inward/record.url?scp=85042749346&partnerID=8YFLogxK
U2 - 10.1155/2017/9361493
DO - 10.1155/2017/9361493
M3 - Article
AN - SCOPUS:85042749346
SN - 2090-0147
VL - 2017
JO - Journal of Electrical and Computer Engineering
JF - Journal of Electrical and Computer Engineering
M1 - 9361493
ER -