TY - JOUR
T1 - A non-enumerative technique for measuring path correlation in digital circuits
AU - Neophytou, Stelios N.
AU - Christou, Kyriakos
AU - Michael, Maria K.
PY - 2012
Y1 - 2012
N2 - The correlation between the physical paths of a digital circuit has important implications in various design automation problems, such as timing analysis, test generation and diagnosis. When considering the complexity and tight timing constraints of modern circuits, this correlation affects both the design process and the testing approaches followed in manufacturing. In this work we quantify the diversity of a set of paths (or path segments), let these be critical I/O paths, error propagation paths for various fault models, or paths traced for diagnostic purposes. Circuit paths are encoded using Zero-Suppressed Binary Decision Diagrams (ZBDDs); the proposed method consists of a sequence of standard ZBDD operations to provide a measure of the overlap of the paths under consideration. The main contribution of the presented method is that, path or path segment enumeration is entirely avoided and, hence, a large number of paths can be considered in practical time. Experimentation using standard benchmark circuits demonstrates the effectiveness of the approach in showing the difference in path correlation between various critical I/O path sets as well as propagation paths during test application.
AB - The correlation between the physical paths of a digital circuit has important implications in various design automation problems, such as timing analysis, test generation and diagnosis. When considering the complexity and tight timing constraints of modern circuits, this correlation affects both the design process and the testing approaches followed in manufacturing. In this work we quantify the diversity of a set of paths (or path segments), let these be critical I/O paths, error propagation paths for various fault models, or paths traced for diagnostic purposes. Circuit paths are encoded using Zero-Suppressed Binary Decision Diagrams (ZBDDs); the proposed method consists of a sequence of standard ZBDD operations to provide a measure of the overlap of the paths under consideration. The main contribution of the presented method is that, path or path segment enumeration is entirely avoided and, hence, a large number of paths can be considered in practical time. Experimentation using standard benchmark circuits demonstrates the effectiveness of the approach in showing the difference in path correlation between various critical I/O path sets as well as propagation paths during test application.
KW - Delay testing
KW - Path diversity
KW - Path similarity
KW - Timing analysis
KW - Zero-Suppressed Binary Decision Diagrams
UR - http://www.scopus.com/inward/record.url?scp=84878473108&partnerID=8YFLogxK
U2 - 10.1007/s10836-012-5333-0
DO - 10.1007/s10836-012-5333-0
M3 - Article
AN - SCOPUS:84878473108
SN - 0923-8174
VL - 28
SP - 843
EP - 856
JO - Journal of Electronic Testing: Theory and Applications (JETTA)
JF - Journal of Electronic Testing: Theory and Applications (JETTA)
IS - 6
ER -