Efficient deterministic test generation for BIST schemes with LFSR reseeding

Stelios Neophytou; Maria K. Michael; Spyros Tragoudas

doi:10.1109/IOLTS.2006.26

Efficient deterministic test generation for BIST schemes with LFSR reseeding

Stelios Neophytou, Maria K. Michael, Spyros Tragoudas

Department of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

We propose a novel method for generating test patterns that can be encoded efficiently using reseeding of LFSR-based schemes for hybrid BIST. Our focus is to reduce the number of deterministic tests while keeping their overall number of specified bits small and, thus, reduce the storage requirements for the LFSR seeds. The proposed solution is based on test function manipulation and generates a compact test set in which individual tests have a high number of unspecified bits. The method uses Binary Decision Diagrams (BDDs) and a modified version of the min-cost max-matching problem on graphs. The obtained experimental results clearly demonstrate the impact of the proposed ATPG algorithm in reducing the on-chip seed storage, when combined with the considered BIST schemes.

Original language	English
Title of host publication	Proceedings - IOLTS 2006
Subtitle of host publication	12th IEEE International On-Line Testing Symposium
Pages	43-48
Number of pages	6
Volume	2006
DOIs	https://doi.org/10.1109/IOLTS.2006.26
Publication status	Published - 2006
Event	IOLTS 2006: 12th IEEE International On-Line Testing Symposium - Como, Italy Duration: 10 Jul 2006 → 12 Jul 2006

Other

Other	IOLTS 2006: 12th IEEE International On-Line Testing Symposium
Country/Territory	Italy
City	Como
Period	10/07/06 → 12/07/06

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10.1109/IOLTS.2006.26

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title = "Efficient deterministic test generation for BIST schemes with LFSR reseeding",

abstract = "We propose a novel method for generating test patterns that can be encoded efficiently using reseeding of LFSR-based schemes for hybrid BIST. Our focus is to reduce the number of deterministic tests while keeping their overall number of specified bits small and, thus, reduce the storage requirements for the LFSR seeds. The proposed solution is based on test function manipulation and generates a compact test set in which individual tests have a high number of unspecified bits. The method uses Binary Decision Diagrams (BDDs) and a modified version of the min-cost max-matching problem on graphs. The obtained experimental results clearly demonstrate the impact of the proposed ATPG algorithm in reducing the on-chip seed storage, when combined with the considered BIST schemes.",

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year = "2006",

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language = "English",

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AU - Neophytou, Stelios

AU - Michael, Maria K.

AU - Tragoudas, Spyros

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N2 - We propose a novel method for generating test patterns that can be encoded efficiently using reseeding of LFSR-based schemes for hybrid BIST. Our focus is to reduce the number of deterministic tests while keeping their overall number of specified bits small and, thus, reduce the storage requirements for the LFSR seeds. The proposed solution is based on test function manipulation and generates a compact test set in which individual tests have a high number of unspecified bits. The method uses Binary Decision Diagrams (BDDs) and a modified version of the min-cost max-matching problem on graphs. The obtained experimental results clearly demonstrate the impact of the proposed ATPG algorithm in reducing the on-chip seed storage, when combined with the considered BIST schemes.

AB - We propose a novel method for generating test patterns that can be encoded efficiently using reseeding of LFSR-based schemes for hybrid BIST. Our focus is to reduce the number of deterministic tests while keeping their overall number of specified bits small and, thus, reduce the storage requirements for the LFSR seeds. The proposed solution is based on test function manipulation and generates a compact test set in which individual tests have a high number of unspecified bits. The method uses Binary Decision Diagrams (BDDs) and a modified version of the min-cost max-matching problem on graphs. The obtained experimental results clearly demonstrate the impact of the proposed ATPG algorithm in reducing the on-chip seed storage, when combined with the considered BIST schemes.

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U2 - 10.1109/IOLTS.2006.26

DO - 10.1109/IOLTS.2006.26

M3 - Conference contribution

AN - SCOPUS:34247233243

SN - 0769526209

SN - 9780769526201

VL - 2006

SP - 43

EP - 48

BT - Proceedings - IOLTS 2006

T2 - IOLTS 2006: 12th IEEE International On-Line Testing Symposium

Y2 - 10 July 2006 through 12 July 2006

ER -

Efficient deterministic test generation for BIST schemes with LFSR reseeding

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