Exploiting Shared-Memory to Steer Scalability of Fault Simulation using Multicore Systems

Stavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael

    Research output: Contribution to journalArticle

    1 Citation (Scopus)

    Abstract

    Current and future multicore architectures can significantly accelerate the performance of test automation procedures depending on the underlying architecture and the scalability of their algorithms. This work proposes a new parallel methodology targeting the fault simulation problem, for shared memory multi-core systems, that maintains scalability with the increase of the number of cores. The method is based on a simple single thread process that allows focusing on the optimization of the parallelization process in different dimensions. Additionally, a number of optimizations are incorporated in the approach to control fault dropping and to avoid unecessary work. The reported experimental results, for both random and deterministic test sets, demonstrate the scalability of the method. As the number of cores increases, the reported speed-up increases proportionally, where comparable recent methods report saturation or even reduction of the obtained speed-up.

    Original languageEnglish
    JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    DOIs
    Publication statusAccepted/In press - 11 Jul 2018

    Keywords

    • fault simulation
    • multi-core systems.
    • parallel processing

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