Typical DSP algorithms require more memory bandwidth. Thus unibus shared-memory systems can support only a handful of processors. The proposed architecture can effectively support 64 digital signal processors (DSPs) in contrast to a maximum of 4 DSPs supported by existing bus-interconnected systems. This significant enhancement is achieved by introducing two small programmable fast memories (Twins) between the processor and the shared bus interconnect. While one memory is transferring data from/to the shared memory, the other is supplying the core processor with data. The proposed architecture eliminates the traditional direct linkage of the shared-bus and processor data bus; thus making feasible the utilization of a wider shared bus. Simulation results show that the fast prefetching memories and the wider shared bus provide additional bus bandwidth to the system, which eliminates large memory latencies; such memory latencies constitute the major drawback for the performance of shared-memory multiprocessors.
|Title of host publication||ICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems|
|Number of pages||4|
|Publication status||Published - 2000|
|Event||7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000 - Jounieh, Lebanon|
Duration: 17 Dec 2000 → 20 Dec 2000
|Other||7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000|
|Period||17/12/00 → 20/12/00|