Fast computations on a low-cost DSP-based shared-memory multiprocessor system

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Typical DSP algorithms require more memory bandwidth. Thus unibus shared-memory systems can support only a handful of processors. The proposed architecture can effectively support 64 digital signal processors (DSPs) in contrast to a maximum of 4 DSPs supported by existing bus-interconnected systems. This significant enhancement is achieved by introducing two small programmable fast memories (Twins) between the processor and the shared bus interconnect. While one memory is transferring data from/to the shared memory, the other is supplying the core processor with data. The proposed architecture eliminates the traditional direct linkage of the shared-bus and processor data bus; thus making feasible the utilization of a wider shared bus. Simulation results show that the fast prefetching memories and the wider shared bus provide additional bus bandwidth to the system, which eliminates large memory latencies; such memory latencies constitute the major drawback for the performance of shared-memory multiprocessors.

Original languageEnglish
Title of host publicationICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems
Pages189-192
Number of pages4
Volume1
DOIs
Publication statusPublished - 2000
Event7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000 - Jounieh, Lebanon
Duration: 17 Dec 200020 Dec 2000

Other

Other7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000
CountryLebanon
CityJounieh
Period17/12/0020/12/00

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    Christou, C. S. (2000). Fast computations on a low-cost DSP-based shared-memory multiprocessor system. In ICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems (Vol. 1, pp. 189-192). [911515] https://doi.org/10.1109/ICECS.2000.911515