Hierarchical fault compatibility identification for test generation with a small number of specified bits

Stelios Neophytou, Maria K. Michael

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Identification of bits that do not necessarily have to be specified in a test set can be beneficial to a number of applications, including low power test, test set encoding and embedding, and test set enriching with n-detect or other fault types properties. This work presents a new method for generating tests containing only a small number of specified bits, while keeping the number of total tests small. The method relies on finding a large number of faults that can be detected by a single test (compatible faults) with a small number of specified bits. Both the total number of specified bits in the test set as well as the number of specified bits per test are minimized. The obtained experimental results show that the proposed methodology can generate compact test sets with an average of 60% of unspecified bits, outperforming existing methods that consider this problem.

Original languageEnglish
Title of host publicationProceedings - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007
Pages439-447
Number of pages9
DOIs
Publication statusPublished - 2007
Event22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007 - Rome, Italy
Duration: 26 Sep 200728 Sep 2007

Other

Other22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007
CountryItaly
CityRome
Period26/09/0728/09/07

Cite this

Neophytou, S., & Michael, M. K. (2007). Hierarchical fault compatibility identification for test generation with a small number of specified bits. In Proceedings - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007 (pp. 439-447). [4358413] https://doi.org/10.1109/DFT.2007.46