Abstract
It has been previously shown that in order to guarantee the temporal correctness of a circuit, only the primitive path delay fault set needs to be tested. However, as in the case of the traditional and simpler path delay fault model, the number of possible faults can be exponential to the circuit size and, therefore, it is only practical to consider the set of critical faults. This work defines critical primitive path delay faults and presents an exact algorithm to identify them, using zero-suppressed binary decision diagrams and newly introduced operators necessary for handling multiple path delay faults. We report the number of critical primitive path delay faults for various criticality thresholds under the bounded delay model. The results indicate that only a small, but still necessary, number of multiple (primitive) faults, which escape testing under the singly testable fault criterion, must be considered in order to guarantee the timing correctness of the circuit.
Original language | English |
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Title of host publication | Proceedings - 28th IEEE VLSI Test Symposium, VTS10 |
Pages | 9-14 |
Number of pages | 6 |
DOIs | |
Publication status | Published - 2010 |
Event | 28th IEEE VLSI Test Symposium, VTS10 - Santa Cruz, CA, United States Duration: 19 Apr 2010 → 22 Apr 2010 |
Other
Other | 28th IEEE VLSI Test Symposium, VTS10 |
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Country/Territory | United States |
City | Santa Cruz, CA |
Period | 19/04/10 → 22/04/10 |
Keywords
- Critical delay faults
- Delay test
- Path delay faults
- Primitive faults
- Zero-suppressed BDDs