Links connecting on-chip components are a major source of power consumption in modern-day on-chip interconnects. Several efforts have henceforth focused on reducing the power consumption, the majority of which efforts target selected links for turning on and off. In this paper we propose an intelligent power management policy for networks-on-chip where links are turned off and switched back on based on a neural network, which processes link utilization as feedback from the system and determines which links are candidates for turning off and back on. The neural network is kept relatively small in terms of area and power consumption, as it is used to forecast the optimal utilization threshold for which underutilized links are turned off.
|Title of host publication||Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011|
|Number of pages||2|
|Publication status||Published - 2011|
|Event||2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011 - Chennai, India|
Duration: 4 Jul 2011 → 6 Jul 2011
|Other||2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011|
|Period||4/07/11 → 6/07/11|