Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems

Stavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael

Research output: Contribution to journalArticle

Abstract

Taking advantage of multicore architectures can provide significant improvement for many design automation problems. However, the parallelization procedure introduces challenges, such as workload duplication, limited search space exploration, and race contention among different threads. In this article, we propose a parallel framework for automatic test pattern generation using shared memory multicore systems that support test generation (TG) for both single-detect and multiple-detect fault models. The framework follows a two-epoch approach, each focusing on a different category of faults, during which a test seed generation is followed by compatibility merging. Various optimization techniques are incorporated in each epoch, designed to achieve higher speedup for the overall TG procedure without impacting much the test set size. A cluster-based approach is also presented, extending the proposed framework to consider multiple-detect fault models without affecting its efficiency. The obtained experimental results demonstrate increased speedup rates compared with the state-of-the-art multicore-based tools while, at the same time, the test inflation problem is restrained. For the multiple-detect extension, these properties are maintained despite the increased workload and the additional constraint of retaining the number of detections for each fault while merging.

Original languageEnglish
Article number8886719
Pages (from-to)553-564
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume28
Issue number2
DOIs
Publication statusPublished - Feb 2020
Externally publishedYes

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Merging
Scalability
Automatic test pattern generation
Data storage equipment
Seed
Automation

Keywords

  • Automatic test pattern generation (ATPG)
  • multicore systems
  • n-detect
  • parallel test generation (TG)
  • test compaction

Cite this

Hadjitheophanous, Stavros ; Neophytou, Stelios N. ; Michael, Maria K. / Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2020 ; Vol. 28, No. 2. pp. 553-564.
@article{cab1bf61baf04c998353d2c2ea0dc67c,
title = "Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems",
abstract = "Taking advantage of multicore architectures can provide significant improvement for many design automation problems. However, the parallelization procedure introduces challenges, such as workload duplication, limited search space exploration, and race contention among different threads. In this article, we propose a parallel framework for automatic test pattern generation using shared memory multicore systems that support test generation (TG) for both single-detect and multiple-detect fault models. The framework follows a two-epoch approach, each focusing on a different category of faults, during which a test seed generation is followed by compatibility merging. Various optimization techniques are incorporated in each epoch, designed to achieve higher speedup for the overall TG procedure without impacting much the test set size. A cluster-based approach is also presented, extending the proposed framework to consider multiple-detect fault models without affecting its efficiency. The obtained experimental results demonstrate increased speedup rates compared with the state-of-the-art multicore-based tools while, at the same time, the test inflation problem is restrained. For the multiple-detect extension, these properties are maintained despite the increased workload and the additional constraint of retaining the number of detections for each fault while merging.",
keywords = "Automatic test pattern generation (ATPG), multicore systems, n-detect, parallel test generation (TG), test compaction",
author = "Stavros Hadjitheophanous and Neophytou, {Stelios N.} and Michael, {Maria K.}",
year = "2020",
month = "2",
doi = "10.1109/TVLSI.2019.2947183",
language = "English",
volume = "28",
pages = "553--564",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",

}

Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems. / Hadjitheophanous, Stavros; Neophytou, Stelios N.; Michael, Maria K.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, No. 2, 8886719, 02.2020, p. 553-564.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems

AU - Hadjitheophanous, Stavros

AU - Neophytou, Stelios N.

AU - Michael, Maria K.

PY - 2020/2

Y1 - 2020/2

N2 - Taking advantage of multicore architectures can provide significant improvement for many design automation problems. However, the parallelization procedure introduces challenges, such as workload duplication, limited search space exploration, and race contention among different threads. In this article, we propose a parallel framework for automatic test pattern generation using shared memory multicore systems that support test generation (TG) for both single-detect and multiple-detect fault models. The framework follows a two-epoch approach, each focusing on a different category of faults, during which a test seed generation is followed by compatibility merging. Various optimization techniques are incorporated in each epoch, designed to achieve higher speedup for the overall TG procedure without impacting much the test set size. A cluster-based approach is also presented, extending the proposed framework to consider multiple-detect fault models without affecting its efficiency. The obtained experimental results demonstrate increased speedup rates compared with the state-of-the-art multicore-based tools while, at the same time, the test inflation problem is restrained. For the multiple-detect extension, these properties are maintained despite the increased workload and the additional constraint of retaining the number of detections for each fault while merging.

AB - Taking advantage of multicore architectures can provide significant improvement for many design automation problems. However, the parallelization procedure introduces challenges, such as workload duplication, limited search space exploration, and race contention among different threads. In this article, we propose a parallel framework for automatic test pattern generation using shared memory multicore systems that support test generation (TG) for both single-detect and multiple-detect fault models. The framework follows a two-epoch approach, each focusing on a different category of faults, during which a test seed generation is followed by compatibility merging. Various optimization techniques are incorporated in each epoch, designed to achieve higher speedup for the overall TG procedure without impacting much the test set size. A cluster-based approach is also presented, extending the proposed framework to consider multiple-detect fault models without affecting its efficiency. The obtained experimental results demonstrate increased speedup rates compared with the state-of-the-art multicore-based tools while, at the same time, the test inflation problem is restrained. For the multiple-detect extension, these properties are maintained despite the increased workload and the additional constraint of retaining the number of detections for each fault while merging.

KW - Automatic test pattern generation (ATPG)

KW - multicore systems

KW - n-detect

KW - parallel test generation (TG)

KW - test compaction

UR - http://www.scopus.com/inward/record.url?scp=85078536704&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2019.2947183

DO - 10.1109/TVLSI.2019.2947183

M3 - Article

AN - SCOPUS:85078536704

VL - 28

SP - 553

EP - 564

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 2

M1 - 8886719

ER -