On the relaxation of n-detect test sets

Stelios Neophytou, Maria K. Michael

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


While defect oriented testing in digital circuits is a hard process, detecting a modeled fault more than one time has been shown to result in high defect coverage. Previous work shows that such test sets, known as n-detect test sets, are of increased quality for a number of common defects in deep sub-micron technologies. n-detect test generation methods usually produce fully specified test patterns. This limits their usage in a number of important applications such as low power test and test compression. This work proposes a systematic methodology for identifying a large number of bits that can be unspecified in an n-detect test set, while preserving the n-detection property, in contrast to any other existing test set relaxation method. The experimental results demonstrate that the number of specified bits in, even compact, ndetect test sets can be significantly reduced without any impact on the n-detect property.

Original languageEnglish
Title of host publicationProceedings - 26th IEEE VLSI Test Symposium, VTS08
Number of pages6
Publication statusPublished - 2008
Event26th IEEE VLSI Test Symposium, VTS08 - San Diego, CA, United States
Duration: 27 Apr 20081 May 2008


Other26th IEEE VLSI Test Symposium, VTS08
Country/TerritoryUnited States
CitySan Diego, CA


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