Scalable parallel fault simulation for shared-memory multiprocessor systems

Stavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


Multicore architectures can significantly accelerate the performance of well-established design and test automation processes, provided that the underlying process is scalable with respect to the system on which it is executed. In this work we concentrate on fault simulation and propose a new parallel process for shared-memory multicore systems, capable of maintaining its scalability as the number of processing cores utilized increases. In order to maximize parallelization, the method utilizes a simple, non-optimized single thread simulation process, which allows for high degrees of freedom to be exploited by three different and combined dimensions of parallelism. Simulation data is distributed to the available cores in a balanced fashion in order to favor speed-up over single-core executions and, ultimately, scalability. The experimental results show that the proposed approach achieves high speed-up rates which, in contrast to comparable state-of the-art methods, increase monotonically with the number of cores demonstrating a highly scalable solution.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE 34th VLSI Test Symposium, VTS 2016
PublisherIEEE Computer Society
ISBN (Electronic)9781467384544
Publication statusPublished - 23 May 2016
Event34th IEEE VLSI Test Symposium, VTS 2016 - Las Vegas, United States
Duration: 25 Apr 201627 Apr 2016


Other34th IEEE VLSI Test Symposium, VTS 2016
Country/TerritoryUnited States
CityLas Vegas


  • ATPG
  • diagnosis
  • fault simulation
  • multi-core systems
  • parallel processing


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