Tackling the complexity of exact path delay fault grading for path intensive circuits

Stelios N. Neophytou, Maria K. Michael

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The high accuracy of the Path Delay Fault model (PDF) is usually sidelined by its high complexity since the number of possible faults can become exponential to the circuit size (even when only critical faults are considered). Thus, fault simulation may require prohibitively large memory resources. In this work we propose a test reordering technique to control the complexity of exact PDF grading when Zero-suppressed Binary Decision Diagrams are used for fault representation. Experimentation on path dense benchmark circuits demonstrates considerable reduction in memory requirements for the PDF grading problem.

Original languageEnglish
Title of host publicationProceedings - 2015 20th IEEE European Test Symposium, ETS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479976034
DOIs
Publication statusPublished - 29 Jun 2015
Event2015 20th IEEE European Test Symposium, ETS 2014 - Cluj-Napoca
Duration: 25 May 201529 May 2015

Other

Other2015 20th IEEE European Test Symposium, ETS 2014
CityCluj-Napoca
Period25/05/1529/05/15

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