Test set generation with a large number of unspecified bits using static and dynamic techniques

Stelios N. Neophytou, Maria K. Michael

Research output: Contribution to journalArticlepeer-review


This work presents two new methods for the generation of test sets with a small number of specified bits. Such type of test sets have been proven beneficial to a large number of test-related applications such as deterministic BIST, low power testing and test set enrichment. The first technique is static, since it considers an initial test set which attempts to relax via test replacement with tests of similar coverage but with fewer specified bits. The second technique is dynamic; it generates a test set from a zero base using a hierarchical fault-compatibility algorithm. Both methods are applicable to any enumerative fault method (linear to the circuit size). The experiments performed using the stuck-at fault model demonstrate the superiority of the proposed methods over comparable existing techniques, in reducing the total number of specified bits per generated test set. The applicability of the generated relaxed test sets is demonstrated for one, out of the many, possible applications, that of deterministic test set embedding. A general framework that integrates the proposed relaxation methods in two popular LFSR-based test set embedding schemes (full and partial reseeding), along with a systematic exploration of related parameters, is proposed. The obtained results show significant reductions in seed storage requirements.

Original languageEnglish
Article number5342413
Pages (from-to)301-316
Number of pages16
JournalIEEE Transactions on Computers
Issue number3
Publication statusPublished - 2010


  • Reliability and testing
  • Test generation
  • VLSI.


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