Two new methods for accurate test set relaxation via test set replacement

Stelios Neophytou, Maria K. Michael

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This papaer presents two different techniques for relaxing a given test set by maximizing the number of unspecified bits in the test set, without compromising the fault coverage or increasing the test set size. The first method replaces each pattern in the test set with another targeting as few faults as necessary. The second method iterates among faults and enforces detection of a fault only by the test resulting in the largest specified bits reduction. Experimental results show increased reduction rates, even when the input test set has been compacted or already contains unspecified bits, when compared to existing methods. The effectiveness of the proposed methods is demonstrated for two popular test set embedding schemes, using the obtained test sets.

Original languageEnglish
Title of host publicationProceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008
Pages827-831
Number of pages5
DOIs
Publication statusPublished - 2008
Event9th International Symposium on Quality Electronic Design, ISQED 2008 - San Jose, CA, United States
Duration: 17 Mar 200819 Mar 2008

Other

Other9th International Symposium on Quality Electronic Design, ISQED 2008
Country/TerritoryUnited States
CitySan Jose, CA
Period17/03/0819/03/08

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