Abstract
This papaer presents two different techniques for relaxing a given test set by maximizing the number of unspecified bits in the test set, without compromising the fault coverage or increasing the test set size. The first method replaces each pattern in the test set with another targeting as few faults as necessary. The second method iterates among faults and enforces detection of a fault only by the test resulting in the largest specified bits reduction. Experimental results show increased reduction rates, even when the input test set has been compacted or already contains unspecified bits, when compared to existing methods. The effectiveness of the proposed methods is demonstrated for two popular test set embedding schemes, using the obtained test sets.
Original language | English |
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Title of host publication | Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008 |
Pages | 827-831 |
Number of pages | 5 |
DOIs | |
Publication status | Published - 2008 |
Event | 9th International Symposium on Quality Electronic Design, ISQED 2008 - San Jose, CA, United States Duration: 17 Mar 2008 → 19 Mar 2008 |
Other
Other | 9th International Symposium on Quality Electronic Design, ISQED 2008 |
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Country/Territory | United States |
City | San Jose, CA |
Period | 17/03/08 → 19/03/08 |